Currently in systems designed to support IEEE Scatter Gather Lists (SGLs), the Input/Output (I/O) to a backend memory controller requires a frame with SGL buffers in an IEEE format. When the buffer sizes are small (say 4 KB), then the number of SGLs will be very high and many chain frames need to be allocated to accommodate all the Scatter Gather Extents (SGEs).
Hardware accelerated write buffering solutions work on small buffers (e.g., 4 KB) and use SGLs to represent the buffers rather than the IEEE SGLS. This would greatly reduce the space requirements to represent all the buffers as well as provide additional flexibility to represent snapshot of a cache at any point of time. Problematically, it would be very inefficient to convert the buffer segment IDs from the SGLs and into IEEE SGLs to communicate with the backend memory controller.
Furthermore, firmware needs to fill fake address(es) in SGEs for performing bitmap data discarding reads. It is much more advantageous if the backend memory controller recognizes these fake addresses and in those cases does not transfer data at all.
Further still, in RAID 5/6 processing there are use cases where some buffers are dirty (BS) and others, like Alias/Temporary buffers are used to read the old data from the drives. It is useful in those cases to have a framework where backend memory controller can identify and skip reading over the dirty buffers such that the RAID 5/6 algorithms can avoid unnecessary frames and buffers allocation for transferring of such data that is not needed and has to be discarded.